A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET flash memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. Flash memory cells effectuate nonvolatile data storage.
Programming, which sets the logical value of a cell to ‘0’, occurs by hot electron injection to the floating gate at about 5–7 Volts. Erasing, which sets the logical value of the cell to “1,” employs Fowler-Nordheim tunneling. Erasure occurs as electrons tunnel through a thin tunnel dielectric layer, by which the charge on the floating gate is reduced. Erasure is driven at about 8–11 Volts.
Prior Art FIG. 1A (not drawn to scale) illustrates a top view of a typical configuration of a plan view of a section of a memory array 100 in a NOR-type of configuration for a memory device. Array 100 is comprised of rows 110 and columns 120 of memory cells. Each of the memory cells are insulated from other memory cells by shallow trench isolation (STI) regions 150.
Effectively, word lines form the gates of the memory cell devices. The control gates of each of the memory cells are coupled together in each of the rows 110 of memory cells, and form word lines 130 that extend along the row direction. Bit lines extend in the column direction and are coupled to drain regions via drain contacts 160 in an associated column of memory cells 120. The bit lines are coupled to drain regions of memory cells in associated columns of memory cells 120.
Source (Vss) lines 140 extend in the row direction and are coupled to the source regions of each of the memory cells in the array of memory cells 100. One Vss line is coupled to source regions in adjoining rows of memory cells, and as a result, one source region is shared between two memory cells. Similarly, drain regions are shared amongst adjoining rows of memory cells, and as a result, one drain region is shared between two memory cells.
Source contacts 145 are coupled to the common Vss lines 140, typically at each 16th device. Each of the source contacts 145 is formed in line with the associated common Vss line to which it is coupled. The source contacts are formed in a column 160, and may be connected with each other. The column 160 is isolated between two STI regions and forms a dead zone in which no memory cells are present.
Vss lines 140 are formed from silicon (Si) substrate by the diffusion of dopants and are thus semiconductors. These semiconducting Vss lines are less conductive than the metal lines used to interconnect drains. With source contacts at, for example, every sixteenth device, current conducted via the relatively resistive Vss lines causes a voltage (e.g., IR) drop between the source contacts and the sources of the individual devices.
Where the Vss IR drop is significant, relatively low Vss conductivity can be problematic. To prevent significant Vss IR drop, conventional Vss lines are made with a heavy implant of dopants, so as to assure sufficient conductivity. However, this conventional solution can also be problematic. The heavy implants needed to make Vss lines of relatively high conductivity can lead to device and scaling problems.
To make Vss lines of sufficient conductivity to minimize IR drop conventionally, the implant dosages used can be high enough for diffusion of implants into the device to occur. Diffusion into the device can adversely affect the performance of the device. Inadequate device performance can correspondingly deleteriously impact the functionality of the memory array. Diffusion into the device can also limit scalability.
One technique for maintaining adequate Vss conductivity is to interconnect Vss lines, thus providing multiple source current paths. Vss lines can be interconnected by implants beneath the adjacent STI regions. The implant must be performed early in the fabrication process, while the STI regions are open, resulting in significant diffusion after the implant.
During further processing however, the regions of diffusion in substrate beneath and between STI in the vicinity of the Vss interconnections can merge, as shown in Prior Art FIG. 1B. This merger 105 of diffusion regions is problematic because it can lead to isolation of the devices from substrate 101. A further problem with this technique is that it can be difficult to maintain the requisite isolation of the drain areas from the Vss implant diffusion.
Although vertical and horizontal reference measurement scales are shown in Prior Art FIG. 1B, the measurements are illustrative only. Implants (e.g., regions of high dopant concentration) 105 are added beneath STI 150, so as to raise the conductivity of Vss lines by interconnecting them.
As shown in Prior Art FIG. 1B, diffusion region 105 effectively interconnects implants 104 under each of the STI regions 150. Problematically, diffusion region 105 isolates device 103. Further, the top of diffusion region 105 is close to drain junction 103. It is possible that the drain will punch through to the diffusion region 105 at moderate voltages.
Diffusion effects associated with implants beneath adjacent STI areas can be severe enough to impact the scalability of the device. A high degree of scalability is desirable for simultaneously increasing performance and decreasing size. The diffusion of the dopants used to raise Vss conductivity however effectively contaminates the channel of the device, isolates devices, and even where controlled, can problematically prevent further scaling.
Conventional amelioration of Vss IR drop by using heavy implants is problematic because associated diffusion affects device performance, which can harm the functionality of the memory array. Further, the diffusion associated with Vss implants under adjacent STI regions can isolate devices and delimit the ability to scale. Such limitations on scaling adversely impact functionality and further miniaturization.